Async

Both codes perform N total random pointer chases — the same amount of work. The first uses one long chain: each load depends on the previous, so the CPU can only have one cache miss in flight at a time (~100ns waiting per miss).

The second splits the work into two independent half-chains. Since p1 and p2 don't depend on each other, the CPU can issue both loads simultaneously using Memory-Level Parallelism (MLP). Two cache misses overlap, effectively halving the total latency.

Modern CPUs have 10-20 Line Fill Buffers (LFBs) that can track outstanding cache misses in parallel. A single pointer chain can only use one at a time. Splitting into K independent chains can use up to K LFBs, giving up to Kx speedup (limited by memory bandwidth).

References:

• Algorithmica - Memory-Level Parallelism
• Wikipedia - Memory-Level Parallelism