Cache Bank Conflict

L1 cache is organized into banks that can be accessed independently. When two simultaneous accesses map to the same bank, one must wait for the other (a bank conflict).

With N=1, the inner loop is very tight and the compiler can optimize the access pattern to avoid conflicts. With N=2, the access pattern to arr1 and arr2 may cause bank conflicts depending on how the arrays are laid out in memory relative to cache bank boundaries.

Note: this effect is highly dependent on the specific CPU microarchitecture and array alignment.

References:

• Agner Fog - Microarchitecture