Control-based Logic Reuse 

// Dedicated: two multipliers, 1 cycle
always @(posedge clk) begin
  result1 <= a * b;
  result2 <= c * d;
end
^ This is Lower Latency?
// Shared: one multiplier, time-multiplexed, 2 cycles
always @(posedge clk) begin
  if (phase == 0) begin
    mult_out <= a * b;
    phase <= 1;
  end else begin
    mult_out <= c * d;
    phase <= 0;
  end
end
^ This is Lower Latency?

* For illustration purposes only, see FAQ for more details.