DRAM Refresh

DRAM cells store data as charge in capacitors, which leak over time. To prevent data loss, the memory controller must periodically refresh every row (tREFI ≈ 7.8µs per row). During refresh, accesses to the affected bank stall.

This causes periodic latency spikes in DRAM access. Pointer chasing through a large random array (defeating prefetching) reveals the effect:

| Percentile | Latency | | --- | --- | | p50 | ~109 ns | | p90 | ~119 ns | | p99 | ~368 ns (3.4x median) | | p99.9 | ~407 ns |

The p99 spikes (~300-400ns) occur roughly every 2-3µs in practice, because modern DRAM controllers interleave refresh across banks — each bank refreshes at 7.8µs, but with multiple banks, a refresh event happens more frequently overall.

References:

• Wikipedia - DRAM Refresh
• What Every Programmer Should Know About Memory