Register Layers 

// 2 register layers
always @(posedge clk) begin
  r1 <= a + b + c;
  result <= r1 + d + e;
end
^ This is Lower Latency?
// 4 register layers
always @(posedge clk) begin
  r1 <= a + b;
  r2 <= r1 + c;
  r3 <= r2 + d;
  result <= r3 + e;
end
^ This is Lower Latency?

* For illustration purposes only, see FAQ for more details.