Pipelining 

// Combinational: 1 cycle, fmax ~ 100 MHz
always @(posedge clk) begin
  result <= (a * b + c) * d;
end
^ This is Lower Latency?
// 3-stage pipeline: 3 cycles, fmax ~ 300 MHz
always @(posedge clk) begin
  stage1 <= a * b;
  stage2 <= stage1 + c;
  result <= stage2 * d;
end
^ This is Lower Latency?

* For illustration purposes only, see FAQ for more details.