Removing Pipeline Register 

// 2-stage: 2 cycles, fmax ~ 500 MHz
always @(posedge clk) begin
  temp <= a + b;
  result <= temp * c;
end
^ This is Lower Latency?
// Single cycle: 1 cycle, fmax ~ 200 MHz
always @(posedge clk) begin
  result <= (a + b) * c;
end
^ This is Lower Latency?

* For illustration purposes only, see FAQ for more details.